CMOS devices are used in many types of applications, such as microprocessors, field-programmable gate arrays (“FPGAs”), complex logic devices (“CPLDs”), and application-specific integrated circuits (“ASICs”). A CMOS device basically has a pair of metal-oxide semiconductor field-effect transistors (“MOSFETs”), one being an n-type transistor, and the other being a p-type transistor, typically separated from each other by an isolation structure, such as an oxide-filled trench or doped guard-band region.
Many integrated circuits (“ICs”) are fabricated in silicon. It is known that changing the lattice spacing of silicon by mechanical stress can increase the mobility of charge carriers (holes and electrons) in the silicon, and thus increase the speed and current-carrying ability of a MOSFET. In a CMOS cell (i.e. a CMOS device having an n-type MOSFET (“NMOS”) paired with a p-type MOSFET (“PMOS”)), performance of the NMOS half-cell is enhanced by applying tensile stress to the channel region, and performance of the PMOS half-cell is enhanced by applying compressive stress to the channel region.
Several techniques have been developed for applying the desired types of stresses to the appropriate halves of a CMOS cell. One technique uses strained silicon films on silicon-germanium buffer layers. However, this is a relatively complex and challenging technique. Another technique introduces strain into MOS devices by localized stress from a silicide cap layer, cap layer, or shallow-trench isolation layers. One approached uses a tensile-stressed silicon nitride etch stop layer to improve performance of the NMOS channel, as well as using a silicon-germanium source/drain to introduce compressive stress into the PMOS channel. However, the process of silicon-germanium source/drain PMOS fabrication typically uses selective epitaxial growth of silicon-germanium and other process steps that increase the cost and complexity of the fabrication process.
Therefore, techniques for applying different types of mechanical stress to each half of a CMOS device is desirable, and is further desirable to be able to incorporate such techniques into standard CMOS fabrication processes.